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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:11:55 10/29/2013 
-- Design Name: 
-- Module Name:    Data_Mem - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Data_Mem is
	port (	clock 	: in std_logic;
				address	: in std_logic_vector (5 downto 0);
				memWrite : in std_logic;
				memRead	: in std_logic;
				writeTerm: in std_logic_vector (15 downto 0);
				readTerm : out std_logic_vector (15 downto 0));
end Data_Mem;

architecture Behavioral of Data_Mem is
    type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
    signal RAM: ram_type;
begin
    
process (clock)
begin
	if clock'event and clock = '1' then
		if memWrite = '1' then
			RAM(conv_integer(address)) <= writeTerm;
		elsif memRead = '1' then
         readTerm <= RAM(conv_integer(address)) ;
      end if;
   end if;
end process;


end Behavioral;

